Schematic Capture Improvements
Marking Multiple Components Fitted/Not Fitted
This release adds the ability to select multiple components on a compiled tab of theschematic sheet and toggle their Fitted /Not Fitted variation state using the icon in the Active Baror the Part Actions » Toggle Fitted/Not Fitted command from the right-click menu of the selection.
Example of toggling Fitted / Not Fitted state for multiple components. Shown here are multiple selected components (C32
- C35
) in their Fitted state. Hover the cursor over the image to see that their variation state changes to Not Fitted after selecting the Toggle Fitted/Not Fitted command.
Placing aReuse Block or Schematic Snippet as a Sheet Symbol
In this release, a reuse block or schematic snippet can be placed on a schematic sheet as a sheet symbol, with the content of this reuse block orschematic snippet placed on an automatically-created child schematic sheet. To do this, select the Place as Sheet Symbolcommand from the Place button drop-down menu or the block/snippettile's right-click menu.
Example of placing a reuse block as a sheet symbol. Shown here is accessing the Place as Sheet Symbol command from the Design Reuse panel. Hover the cursor over the image to see the content of the reuse block placed on the automatically created child schematic sheet.
The Place command places a reuse block or schematic snippet right on the active schematic sheet like it was before.
PCB Design Improvements
Custom Pad Shapes
This new feature allows you to create custom shape pads in PCB designs andPCB footprints.
An example component placed in a PCB design and featuring pads of a custom shape.
- Custom pad shapes can be created by converting placed regions or a closed outline, or directlyby selecting the newCustom Shapeentry from theShape drop-down in thePad mode of theProperties panel.
- A placed custom shape pad can be edited by using the Outline Vertices table in the Properties panel, the Edit Shape button in the Properties panel, or thePad Actions »Modify Custom Pad shapecommand from the pad's right-click menu.
- Thermal relief connections are supported for custom shape pads to both solid and hatched polygons. You can choose to use conductors from each side of the pad region or use a selected number of conductorsso that they intersectthe pad origin at a specified angle.
- The query language
IsCustomPadShape
andIsCustomPadShapeOnLayer
keywords can be usedto facilitate custom shape pad selection, scoping design rules, etc.You can also use thePadShape_AllLayers
,PadShape_TopLayer
,PadShape_BottomLayer
, andPadShape_MidLayer<n>
keywords with the'Custom Shape'
string to get pads ofcustom shape on a specific layer. - Custom pad shape templates are supported by thePCB Pad Via Templatespanel. Atemplate name for a custom pad shape begins with 'u'.
- When generating your manufacturing output (Gerber, ODB++), a custom pad shape is now output as a true contour with arcs.
- Custom pad shapes are supported when saving/loading the PCB in ASCII format.
- The Mentor Expedition®Importer supports custom pad shapes.When such pads are imported in Altium Designer, they are imported as pads of the custom shape type.
To learn more about this functionality, seeWorking with Custom Pad Shapes.
This feature is in Open Beta and is available when the PCB.Pad.CustomShape
option is enabled in theAdvanced Settings dialog.
Added Max Current and Resistance Values for Tracks, Arcs,and Vias
Calculated Max Current and Resistance values are now provided in the Net Information region of theProperties panel for a selected Track, Arc, or Via object.
The Max Current and Resistance values are now provided in Track, Arc, and Via modes of the Properties panel.
Max Current- determined from the IPC-2221A formula (Section 6.2):
I = k* ΔT0.44 * A0.725
where:
I = current [amps]
A= cross-sectionalarea [sq mils] (trace width * layer stack copper thickness, or Abarrel, as shown below)
ΔT= allowable temperature rise above ambient [°C]
k = constant, such that:
k = 0.048 for outer layers
k = 0.024 for inner layers
When multiple objects are selected, for example an entire net, the Max Current for that net is the smallest individual Max Current value of the selected objects.
Resistance- determined from the derived formula:
R = (ρ * L / A)
where:
R = resistance [Ω]
ρ= resistivity of copper [Ω*mm2/m]
L = trace length [m](or Via Length, as described below)
A = cross-sectional area =T * W [mm2](or Abarrel, as shown below)
T = trace thickness (from layerstack) [mm]
W = Trace width [mm]
Assumptions:
- Ambient temperature =22°C
- Allowable temperature rise =20°C
- Thruhole copper wall thickness = 0.018mm
- Resistivity of copper = 0.017 Ω*mm2/m
The total Resistance of the selected objects is the sum of the resistance of the individual objects.
Via Barrel Cross-Sectional Area - determined as follows:
Abarrel = AViaHoleSize - AFinishedHoleSize
Abarrel = [ π * (ViaHoleSize/2)2] - [π * ((ViaHoleSize - 2 * ViaWallThickness)/2)2]
Abarrel = π (ViaHoleSize *ViaWallThickness -ViaWallThickness2)
Via Length = distance from the center of entrancelayer to the center of exitlayer, as shown above
Notes - via length in these calculations is dependent on the via belonging to a net and the layers used by the connected tracks. Aselected via with no net assignedwill display the layer-edge to layer-edge length instead of the layer-center to layer-center length. Also, a via with a net assigned but no connected tracks will display a length of zero.
Added Diff Pair and xSignal Information
For copper objects on a PCB, the information on the Differential Pair, Differential Pair Class, xSignal, and xSignal Class is now shown in the Properties panel if the selected object is part of a differential pair or an xSignal.
The Properties panel now shows comprehensive information on the differential pair and xSignal of which the selected object is a constituent part.
Click a link in the Net Information region to open thenet/differential pair/xSignal in the PCB panel.
Improved Working with Single-line and Multi-line Text Objects
You can now switch between single- and multi-line editing modes using the String and Frame buttons in the Properties panel for a selected Text object. When using single-lineString mode, use the Text field to type in the value or use the drop-down to select a special string. When in multi-lineFrame mode, the text object properties operate as before.
The String and Frame editing modes are now provided in the Text mode of the Properties panel.
Rendering of Self-intersected Regions
This feature allows rendering of self-intersecting regions in the PCB editor in the same way as they will be exported to fabrication outputs (Gerber/ODB++).
Example of a self-intersecting region selected in the PCB editor design space. Hover the cursor over the image to see this region in the generated Gerber output.
This feature is in Open Beta and is available when the PCB.Rendering.SelfIntersectedRegions
option is enabled in theAdvanced Settings dialog.
Net Priorities When Pasting Objects
The behavior of net assignment for objects pasted in a PCB design has been improved by introducing the priorities of different object types.
When an object is being pasted on a copper layer, and it overlaps a set of objects of different types when pasted, a net of the highestpriority object will be assigned to the pasted object.The priorities are as follows (1 is the highest priority):
- Pad
- Fill
- Region
- Track
- Arc
- Via
- Polygon Pour
A net of the highest priority object is assigned to a pasted object. Shown here is an object (track) pasted over a set of objects of different types with different nets assigned. Since the pad is the object of highest priority in this set, its net (Pad_Net
) will be assigned to the pasted object. Hover the cursor over the image to see the result.
When an object is pasted on a copper layerand it overlaps a set of objects of the same typewhen pasted, a net of the object that is under the cursor when clicking to paste the object will be assigned.
A net of the object under the cursor is assigned to a pasted object. Shown here is an object (track) pasted over a set of objects of the same type (pads). Since pad 2 is the object that is under the cursor when clicking to paste the object, the net of this pad (Pad2_Net
) will be assigned to the pasted object. Hover the cursor over the image to see the result.
When a set of physically connected objects is pasted on a copper layerand objects of different types in this set overlap existing objects with different nets,a net of the highestpriority object in this set will be assigned to all pasted objects. The above priorities are applied in this case.
The net assigned to the highest priority object is assigned to the set of the physically connected objects. Shown here is a set of connected objects (from left to right: Fill, Region, Track, Arc, Via, and Polygon Pour) pasted over objects (vias) with different nets assigned. Since the fill is the object of highest priority in this pasted set, the net assigned to it (Via1_Net
) will be assigned to each object in this set. Hover the cursor over the image to see the result.
This feature is in Open Beta and is available when the PCB.CopyPaste.NetsPriority
option is enabled in theAdvanced Settings dialog.
The New Version of Open CASCADE Technology
This release sees the introduction of the new Open CASCADE Technology 7.5 version. Using the updated version allows to increase the performance of loadand export the STEP 3D-model files, especially for large files.
This feature is in Open Beta and is available when the PCB.OpenCascadeLatestVersion
option is enabled in theAdvanced Settings dialog.
Detecting Dead Copper Primitives in Net
Copper layer objects with a net assignment but not connected toany Pad object of the same net and not connected with other objects of the same net with connection lineswill be checked.To run the check, clickTools » Design Rule Check.Ensure theReport Dead Copper larger thanoption is enabled on theReport Optionspage of theDesign Rule Checkerdialog. (The value field of this option applies to the plane. All other objects are checked regardless of size.) This option isenabled by default.Errors are flagged as anUnrouted Net Constraintin theMessagespaneland the Design Rule Verification Report.
This feature is in Open Beta and is available when the PCB.Rules.DeadCopperInNet
option is enabled in theAdvanced Settings dialog.
Prevent Self-Intersections
When placing or editing a polygon-shaped object (e.g. Polygon Pour or Regions) and a self-intersection of its contour occurs, a warning opens to alert you to this fact. You can Proceed with the current shape or click Revertin the warning to roll back to the last non-intersecting vertex.
This feature is in Open Beta and is available when the PCB.PreventSelfIntersections
option is enabled in theAdvanced Settings dialog.
Data Management Improvements
Added BOM Compare Functionality
The features for comparinglocally saved documents of an Altium 365 Workspace project with a commit or release of this project have been extended by implementing support for BOM documents. Select a command from the Save to Server dialog, theProjects panel, or the Project History viewto select arequired data set with which the locally-saved documents should be compared.
The BOM compare commands can be accessed from the Projects panel.
To learn more about the local document comparison feature, refer to theCompare Local Documents with Commit or Release Datasection of the Working with Documentspage.
Added Output Job to Default Templates
An Output Joboption has been added to the Data Management - Templates page of the Preferences dialog, which allows an output job template to be added to the connected Workspace. The option can be accessed from the Add drop-down as shown below.
Circuit Simulation Improvements
Added Support for Digital Nodes
In this release, support for digital nodes has been implemented. Digital nodes are the nodes of the circuit connected only to pins of components with digital models. A new Digital wave type was added to represent logical levels (0, 1, undefined) of digital output waves.
- The components of the
Simulation Generic Components
library are now digital. That allows using these components in both analog and digital calculations. -
To add a digital wave to an outputplot, select Digital from the Waveforms drop-down in the Add Output Expression dialog. Digital waveforms are prefixed with
d
.Note that nodes to which both analog and digital componentsare connected can be plotted as a digital signal orvoltage.
(Video) How To Define and Place Vias in Altium Designer? -
The undefined state of a digital signal is denoted with a double line on plots and with the
X
numeric value. -
Support for the PSpice digital stimulus generatorhas also been implemented.
This feature is in Open Beta and is available when the Simulation.DigitalNodes
option is enabled in theAdvanced Settings dialog.
Defining a New Simulation Model Using the Sim Model Dialog
In this release, the Sim Model dialog is now used to define a new or edit a referenced simulation model for a Workspace library component being created or edited in the Component Editor in its Single Component Editing mode. That allows you to quickly define a reference to a simulation model from different sources.
Use the Sim Model dialog to define a new simulation model for a Workspace library component.
This feature is in Open Beta and is available when the Simulation.NewSimModelDialogForServerComponent
option is enabled in theAdvanced Settings dialog.
Improved UI for Managing Output Expressions
A number of features and controls havebeen implemented in the Simulation Dashboard panel for better management of output expressions from the panel:
-
Added aplot number drop-down and a color icon that allows defining the number of an existing plot (or creating a new one)and the wave color without opening the Add Output Expression dialog.
- When an output expression field is currently active in the panel (the text cursor is within the field), clicking the + Add control at the bottom of the Output Expression region will add a new output expressionbelow the active expression. The Plot Number and Axis Number values of the active expression will be inherited by the new expression.
-
The order of output expression lines can now be changed using the drag-and-drop technique. Click and hold the left mouse button on the free space of an output expression line to move it up or down in the list.
New Global Parameters Settings
TheGlobal Parameters tab of the Advanced Analysis Settings dialog now displays calculated values of global parameters along with their formulas. If a global parameter is defined using a formula, its valuewill be shown in the Value column, with theformula in parenthesis next to the value.
The Global Parameters tab of theAdvanced Analysis Settings dialog now shows both calculated values and the formulas of global parameters.
Auto-Assignment Messages Display in Messages Panel
Messages relating to the auto-assigned simulation modelsare now presented in the Messages panel. Click the Edit Model control for an auto-assigned model to open the Sim Model dialog and also show messages related to this model.
An example of messages related to an auto-assigned simulation model.
Features Made Fully Public in Altium Designer 22.8
The following features have been taken out of Open Betaand have transitioned to Public in this release:
- Auto-Assign Simulation Models for Components Without Models - available from 22.7
- PCB Health Check Monitor - available from 22.5
- New Design Reuse Functionality - available from 22.4
- Length Tuning Relative to a Chosen Target xSignal - available from 22.3
FAQs
What is new in Altium? ›
New Design Reuse Functionality
When connected to your Altium 365 Workspace, the new content of the Reuse Block type can be created, used, and managed, as well as Workspace-based schematic and PCB snippets. The new Design Reuse panel provides access to reuse blocks and both Workspace-based and local snippets.
Altium's intuitive user interface makes it easy to get started, even if you're new to printed circuit board design. Behind this simple interface lies extreme design power.
Is Altium better than Eagle? ›Comparing these two software, Eagle has better options when comes to integrated design or team collaboration. Better options are available in Eagle in case of hardware based project whereas on the other hand, the user interface of Altium is more reliable and powerful.
What is the difference between VIA and pad in Altium? ›The key difference between a via and a pad is that as well as being able to span all layers of the board (top to bottom), a via can also span from a surface layer to an internal layer or between two internal layers.